W-CMP for sub-micron inverse metallisation

Chemical Mechanical Polishing (CMP) of tungsten for an inverse metallisation scheme is investigated. The influence of CMP parameters on removal rate and uniformity is studied. The main effects on the removal rate are the applied pressure and the rotation rate of the polishing pad. To the first order Preston's equation is obeyed. The uniformity is best with equal rpm of pad and wafer and with perforated pads. Also, pattern density effects of CMP of W/PETEOS are investigated. Dishing increased at larger W-linewidth. Oxide erosion increased at larger pattern density and smaller W-linewidth. Electrical measurements on submicron (0.4 and 0.5 ¿m) test structures yielded good CMP results

Modelling of dishing for metal chemical mechanical polishing

In this paper, a physical model for the development of dishing during metal chemical mechanical polishing (CMP) is proposed. The main assumption of the model is that material removal occurs predominantly at the pad/wafer contacts. The distribution of pad/wafer contact size is studied first. This distribution is used as an input for a model of the dependence for the material removal rate on the line width. A relation that describes the development of dishing as a function of overpolish time will be presented. The model describes to a great accuracy the observed dishing effects, using one free paramete

High-Performance Deep SubMicron CMOS Technologies with Polycrystalline-SiGe Gates

The use of polycrystalline SiGe as the gate material for deep submicron CMOS has been investigated. A complete compatibility to standard CMOS processing is demonstrated when polycrystalline Si is substituted with SiGe (for Ge fractions below 0.5) to form the gate electrode of the transistors. Performance improvements are achieved for PMOS transistors by careful optimization of both transistor channel profile and p-type gate workfunction, the latter by changing Ge mole fraction in the gate. For the 0.18 ¿m CMOS generation we record up to 20% increase in the current drive, a 10% increase in the channel transconductance and subthreshold swing improvement from 82 mV/dec to 75 mV/dec resulting in excellent ¿on¿/¿off¿ currents ratio. At the same time, NMOS transistor performance is not affected by gate material substitutio

Thin SIMOX SOI material for half-micron CMOS

\u3cp\u3eThe properties of half-micron CMOS devices fabricated on thin film SIMOX SOI with different material quality will be presented. The gate oxide quality, diode leakage current and breakdown voltage of transistors will be shown. The influence of LDD dope and TiSi\u3csub\u3e2\u3c/sub\u3esalicide on the parasitic bipolar transistor breakdown is presented. Temperature measurements on SOI and bulk transistors are presented which show an increased heating effect for thin film SOI transistors.\u3c/p\u3

Chemical mechanical polishing for planarisation of advanced IC processes

\u3cp\u3eAn CMP process will be presented which is optimised for low layout sensitivity and good uniformity. The best results were obtained by using a stack of two polishing cloths, instead of a single cloth. This results in a better planarisation capability while improving the uniformity compared to a single hard polishing cloth. The feasibility of the novel CMP process was demonstrated on a 64k SRAM.\u3c/p\u3

Soft breakdown triggers for large area capacitors under constant voltage stress

\u3cp\u3eThis work quantitatively compares breakdown triggers for constant voltage stress of large area NMOS capacitors (up to 10 mm\u3csup\u3e2\u3c/sup\u3e) with 1.8 to 12 nm gate oxide thickness (with negative V\u3csub\u3eG\u3c/sub\u3e). We conclude that in the studied range, breakdown is identified more reliably with a current step trigger than through increased current fluctuation (RMS). We also present data filtering algorithms that significantly enhance the ratio between the breakdown signal and background noise level.\u3c/p\u3

Comparison of soft-breakdown triggers for large-area capacitors under constant voltage stress

\u3cp\u3eThis work quantitatively compares soft breakdown identification methods for constant: voltage stress of large-area nMOS capacitors (up to 10 mm\u3csup\u3e2\u3c/sup\u3e) with 1.8- to 12-nm gate-oxide thickness with negative gate voltage. We conclude that in the studied range, breakdown is identified more reliably with a current step trigger than through increased current fluctuation. We present a method to quantify the system background noise, and show results of data filtering algorithms that significantly enhance the ratio between the breakdown signal and background noise level. Index Terms-CMOS, reliability, soft breakdown, TDDB.\u3c/p\u3

Positive oxide-charge generation during 0.25 µm PMOSFET hot-carrier degradation

\u3cp\u3eA new hot-carrier degradation mechanism becomes important in 0.25 µm PMOSFET's. Hot-hole injection generates positive oxide charge near the drain. We determine the time dependence and the oxide-thickness dependence and we show a considerable enhancement of this degradation mechanism for nitrided gate oxides. For many bias conditions and many geometries, the time dependence of PMOSFET degradation can be successfully described by a summation of the time dependences of three separate degradation mechanisms: generation of interface states, negative oxide charge and positive oxide charge.\u3c/p\u3

Conduction and trapping mechanisms in SiO2 films grown near room temperature by multipolar electron cyclotron resonance plasma enhanced chemical vapor deposition

Silicon dioxide layers with stoichiometric composition and excellent electrical properties were deposited at a substrate temperature of 60 degreesC with an electron cyclotron resonance plasma source. This work is focused on determining the electrical conduction and trapping mechanisms of the deposited films. From the temperature dependence of current density-electric field characteristics, Fowler-Nordheim tunneling was found to be the dominant conduction mechanism in SiO2 films obtained with low silane flow and at low pressure. For layers deposited with higher silane flows and higher pressures, the current at low biases is highly dependent on temperature. Positive charge was measured at the Si/SiO2 interface during low electric stress, while electrons were trapped at the interface for electric fields higher than 7 MV/cm. Constant current stress measurements confirmed that low silane flow and low total pressure are suitable deposition conditions for obtaining a film comparable to thermally grown oxide from the reliability point of view